This invention relates generally to integrated circuits, and more particular to integrated circuits utilizing CMOS transceiver technology.
Tranceivers (transmitters/receivers) are used in integrated circuits to communicate with circuitry off and/or on the integrated circuit chips. However, transceivers of the prior art tend to be rather complex, which increases the “footprint” on the integrated circuit chip. Prior art transceivers also have power, performance and cost issues.
Considerable research effort has focused on implementing the physical layers of Gigabit Ethernet, Fibre Channel, IEEE 1394, network switch, etc. The major goal is to give the physical layer a high bandwidth transmission for digital data over a long cable with a low bit error rate (BER). As more transceivers operate at higher frequencies and over longer cables, the signal frequencies tend to come close to the channel bandwidth. Bandwidth limitation in the channel causes signal degradation, in the form of inter-symbol interference (ISI). Signal degradation shows up in the eye diagram as eye-closure: the center of the eye is smaller in both time and signal amplitude. Eye-closure causes higher BER since it restricts successful data-detection to a smaller time interval.
According to IEEE std 802.3z, Gigabit Ethernet standard, the receiver shall operate if the total jitter of data transition is less than 71% of the bit time, where deterministic jitter takes up 45% and random jitter, 26%. Deterministic jitter is also referred to as systematic jitter and is caused mostly by ISI and duty-cycle distortion. Random jitter is also referred to as nonsystematic jitter and is generated by a number of noise sources such as thermal noise, power supply noise, substrate noise, etc. Random jitter is Gaussian in nature, while deterministic jitter is due to non-Gaussian events.
Random jitter is generated in both the transmitter and receiver. A transmitter clock is generated by a transmitter-side phase locked loop (PLL) or delay locked loop (DLL). Since this clock switches the serializer, the outgoing data stream inherits the jitter component of the PLL or DLL generated clock. The receiver clock samples the data with its own jitter component. Thus, the equivalent jitter is the sum of both jitter components. As the transceiver operates at higher frequencies and the bit time becomes shorter, the random jitter will occupy a greater portion of the bit time and then the eye opening will narrow. Therefore, for a lower BER, jitter should be reduced in both the transmitter and receiver as the frequency increases.
In general, a clock recovery circuit takes a sequence of times at which a transition edge of a pulse crosses some threshold voltage and averages the times to extract the real input pulse timing. This averaging process makes the clock recovery circuit tolerant to input jitter. Jitter tolerance is a very critical requirement for clock recovery circuits. With the same circuit and process the jitter tolerance will be dependent on the transceiver architecture.
Currently, many transceivers are designed to be a macro-cell of an ASIC standard cell library as well as a stand-alone component. Thus, both small area and low power consumption become essential in the transceiver design. In order to measure the BER of a transceiver in an operating frequency, a test board with a small number of field programmable gate array (FPGA) chips is required. The FPGA in the transmitter side generates an appropriate bit sequence, and that in the receiver monitors the sequence and measures the BER. If built-in self-test (BIST) capability is included on chip, this will take the place of the FPGAs. The BIST can lower the test cost and cover the entire frequency range of the transceiver. As mentioned above, when designing a high-speed transceiver with a low BER, jitter reduction and jitter tolerance of the architecture are the most important design issues. Low power consumption, small chip area, and testability are also design concerns. In these types of systems, the PLL and a voltage controlled oscillator (VCO) within the PLL are known sources that produce jitter to the clock signals.
For a given tuning range of a VCO, as the chip supply voltage scales down with technology advancement, a VCO gain (Kv) grows larger. However, too large a Kv induces detrimental problems in a PLL, while also causing large jitter and a narrow pumping current range. In a realistic phase detector and charge pump design, the control voltage of a VCO is disturbed by parasitic currents due to coupling and charge sharing. So, a large Kv induces a large jitter. Also, since the current range of a charge pump is inversely proportional to Kv, a large Kv makes the pumping current range narrow, possibly causing instability in varying PVT conditions.
It would therefore be desirable to provide an integrated circuit transceiver that has a small footprint, operates at high frequencies, and which has superior power, performance and cost advantages over transceivers of the prior art. It is also desirable to reduce jitter produced by the transceiver components.